Multilayer ceramic chip capacitors (MLCC) are one of the most widely used types of ceramic capacitors today. And not without reason: They have been optimized significantly with regard to their maximum nominal C values and also ever lower ESR values (Equivalent Series Resistance). However, this is accompanied by ever greater drifts, especially with respect to DC voltage, temperature, and time (Fig. 1).
Class 2 ceramic capacitors have now reached such high capacitances which repeatedly leads to miscalculations of their actual capacitance during operation. It is often not known how the components behave in the real application and why they vary so much as soon as voltage is applied. An important electrical parameter responsible for this is the DC bias.
DC bias effect
The DC bias effect can best be demonstrated in the laboratory. TDK used a 3216 X7R 1µF capacitor with a nominal voltage of 25V for the tests and connected it to an LCR meter. This displayed 1µF at 0V. If 25V was applied, a capacitance loss of more than 40% compared to the nominal capacitance values could be detected.
The reason for this is the actual structure of the ceramic capacitors: Their dielectric material is obtained from barium titanate, a ferromagnetic material whose molecules adhere to the structure barium2+, oxygen2-, titanium4+. In this case, titanium is in the middle. This molecular structure has a cubic crystal structure above the Curie temperature (approx. +125°C) and changes into a tetragonal crystal structure below the Curie temperature. This generates a polarity known as dipole, where one side of the axis is more positive and one is more negative than the other.
Without the application of a DC voltage, there is no electric field and the dipoles arrange themselves randomly in the entire crystal structure (spontaneous polarization). Meanwhile, the dielectric constant is high, which also results in high capacitance.
If a low DC voltage is now applied, the electric field influences some of the dipoles due to the polarization. These start to align themselves parallel to the electric field, which reduces the capacitance.
If a higher DC voltage is applied, several dipoles align themselves parallel to the electric field and the capacitance decreases continuously. When the nominal voltage is applied to the capacitor, the capacitance level may drop by up to 50% or more from the nominal capacitance level (Fig. 2).
The effect of DC bias on the capacitance of class 2 ceramic capacitors cannot be avoided. However, there are ways to cope with it.
Improving circuit designs
The comparison of several DC bias curves of class 2 capacitors shows which possibilities exist in order to reduce the effect in the application:
With a capacitor featuring 1nF and a nominal voltage of 16V, the capacitance decreases by almost 9% at 10V and by 21% at 16V. This could already be unacceptable for some designs. With the same capacitor featuring a nominal voltage of 25V, the capacitance at 10V only decreases by 2%.
This is due to the fact that the dielectric layers in ceramic capacitors are thicker at higher nominal voltages. A thicker dielectric means a weaker electric field that affects fewer dipoles.
The capacitance change for a 470pF capacitor of the same package size at 10V is only 0.6%. If the design allows two of these capacitors to be connected in parallel, this would be a possible solution for the DC bias effect. Since lower capacitance values allow thicker dielectric layers.
Sometimes capacitors with the same capacitance value are also available in a larger package. They also usually have thicker dielectric layers and thus better DC bias behavior.
Practical example: DC bias not considered
What can happen if the DC bias is not considered in an application is shown by a practical example: One customer used a 0805 4.7µF X5R multilayer ceramic capacitor with 25V and a nominal tolerance of 10% as well as measuring parameters of 1kHz at 1Veff. The customer complained that the components were defective, as their C-value at 14.5V was only approx. 1µF and not approx. 1.5µF as with the ‘golden’ sample. This resulted in a ripple signal at 15V, which in turn led to an undervoltage at the IPM driver power supply and poor MOSFET commutation, which ultimately resulted in an overcurrent at the motor windings.
It turned out that the capacitor manufacturer had used two different raw material mixtures to maintain the reliability of supply. At 14.5V, one mixture displayed values of approx. 1µF, the other approx. 1.5µF; in other words, both met the characteristic data (Fig. 3 and 4). The customer’s argument was made by basing his sample on the components with the higher values without examining the reason for the difference or taking into account the corresponding general diagram. The threshold value in the application was approx. 1.25µF. Initially, the customer just happened to receive the components with lower DC bias. When the customer finally received the ones with the more pronounced DC bias, it manifested itself in misbehavior of the circuit.
The example shows that it is particularly important in shortage situations to know and consider the real requirements of the individual functions in an application and the behavior of the MLCCs. It is essential to note: Which actual voltage is necessary? Which temperatures need to be considered in practice? Where are the threshold values of the effective capacitance value? In case of doubt, developers should seek the advice of the capacitor manufacturer or the distributor, especially if there are relatively clear deviations from the characteristic data and diagrams, as these are not guaranteed in contrast to specification data.
In this case, in particular, it is recommendable to check in advance, using the DC bias curve of the capacitor, whether the capacitance is acceptable for the actual operating voltage. If this is not the case, capacitance loss can be minimized in three ways:
- Through parallel connection of two or more capacitors with a lower capacitance value
- Through selection of a capacitor with a higher nominal voltage
- Through a capacitor with a larger package.
All three methods usually have thicker dielectric layers that help minimize capacitance loss due to DC bias. This avoids technical problems and provides developers with more alternatives to choose from.