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Bridge ICs - A Translator for Images and Videos on Any Device


Displays are being found in more and more devices – even the refrigerator, in smartwatches, and in the automobile. Users expect crystal-clear playback with zero judder – on any medium. Bridge ICs are used to make this possible, even with different standards.

The most well-known differential method for fast transfers of large amounts of data at rates of up to several Gbit/s - and thus for image and video content - is LVDS (low-voltage differential signaling technology). Developed by National Semiconductor, LVDS was standardized as EIA-644 by the EIA (Electronic Industries Association). It is a free and open standard that is used by many IC suppliers.

LVDS is a unidirectional connection that works very energy-efficiently. This technology uses the voltage differential between two copper cables to transfer information. The LVDS transmitter encodes up to 24-bit data based on an input clock over four serial differential pairs (see Figure 1). A terminating resistor prevents reflection back to the signal source.

Because LVDS works with low voltages of under 3.3V, the technology requires little current and generates only minor electromagnetic interference. Common-mode voltages generating an electromagnetic wave are eliminated by the differential.

LVDS only describes the physical level; several other communication standards are based on it, including FPD-Link (Flat Panel Display), FPD-Link II & III, MIPI (Mobile Industry Processor Interface) and DVP (Digital Video Port).

LVDS with FPD-Link

When we talk about LVDS, we usually mean the FPD structure. FPD-Link was developed alongside LVDS by National Instruments and remains the standard today for the transmission of graphical and video data between notebooks, tablet PCs or LCD televisions and their display.

FPD-Link chipsets consist of transmitters (TTL to LVDS) and receivers (LVDS to TTL) that support 18 and 24-bit color displays. At the TTL level, the RGB data and control data from the graphics controller is transmitted to the inputs of the FPD-Link transmitter. It acts as a multiplexer (mux) for the parallel TTL data and converts it to the serial LVDS standard. The LVDS data is sent to the outputs of the transmitter via the cable connecting the mainboard to the display. At the FPD-Link receiver on the display, they are deserialized (demuxed), which means that they are converted back into TTL signals and sent to the inputs of the timing controller. Multiplexing the parallel TTL signals allows higher-speed data to be transmitted over a narrow-band interface. Even so, the requirements of high-bandwidth communications are met.

Figure 2 shows the structure of an FPD-Link with four LVDS wire pairs. Three of the four cables transmit the graphics and video signal, while the fourth conveys the LVDS clock signal. The mux circuit serializes the parallel graphics and video signal and transmits it over the differential pair. Thus, only 3 cables are needed as opposed to the 22 otherwise needed, and there is also an improvement in electromagnetic compatibility.

FPD-Link chipsets are available with falling and rising edges and programmable data import to provide a convenient interface with a variety of graphics and LCD panel controllers. The 5V or 3.3V chipsets support a frequency range of 20 to 65MHz.


The MIPI Alliance has specified six types of interfaces in mobile, networked devices: for the physical level, multimedia, chip-to-chip or interprocess communication, device control and data management, system debugging and software integration. Each specification satisfies the most important requirements of these devices: low energy consumption, high bandwidth and low electromagnetic interference.

DSI (Display Serial Interface) and DSI-2 are the MIPI interfaces between one or several displays and the application processor. They define a serial bus and a communication protocol for data transfer between the host, the image data source, and the target application. They were developed to enable lower-cost display controllers for mobile devices such as smartphones, laptops and tablet PCs, wearables, augmented reality applications and vehicle instrument panels.

The Physical Layer

MIPI-DSI is based on the physical layer MIPI D-PHY. It is used to connect megapixel cameras and high-resolution displays with an application processor. A clock-forwarding, synchronous link is used here that combines high-speed data transmission with low power consumption as well as high resistance to interference and high jitter tolerance with low costs (Figure 4).

At the physical layer, DSI specifies a serial point-to-point high-speed differential signal bus. It encompasses a high-speed clock lane and one or several data lanes. Each lane covers two wires due to the differential signal use. All lanes run from the DSI host to the DSI device with the exception of the first data lane (Lane 0). It is capable of a bus turnaround operation (BTA) that allows the direction of transmission to be reversed. When several lanes are used, they transmit data in parallel, thus allowing four bits to be transmitted simultaneously when four lanes are being used.

The connection operates either in low-power mode or high-speed mode. The transition between the two modes is done with minimal latency. In low-power mode, the maximum speed clock is disabled and the signal clock information is embedded in the data. The data rate is not enough to control a display, but can be used to send configuration information and commands.

In high-speed mode the high-speed clock is used at frequencies of several tens of Megahertz up to over a Gigahertz as a bit clock for the data lanes. The clock speeds vary depending on the requirements of the display. Because only a low voltage is required for the signal output and the data is transmitted in parallel, high-speed mode can operate with minimal power usage.

Further DSI Layers

In terms of lane management, the transmitter distributes the transmitted data over one or several of the four lanes, depending on bandwidth requirements. For mapping - the method of determining which bit is transmitted over which lane - the standards from VESA (Video Electronics Standards Association) and JEIDA (Japan Electronic Industry Development Association) are well-established.

The low-level protocol layer defines how the bits and bytes are organized into packets and which bits constitute the header and payload. This is also where error-checking is performed.

At the application level, data from the layer beneath is finally translated into pixels or commands.


A comparison of LVDS and MIPI DSI reveals only one common factor: both use four lanes. LVDS only transmits the video/image signal though, for which the RGB-TTL signal is converted into an LVDS signal using the SPWG (Standard Panels Working Group) or JEIDA standard. MIPI DSI on the other hand can transmit not only video/image data but also command signals. Both signals can be controlled in accordance with the specific handshake sequence and rules.

Bridge between DSI and LVDS

If the application process doesn't support a standard or does not have enough lanes to connect to a display module, a bridge IC can create the corresponding interface between the video output of the processor and the input of the display module, the camera or other peripheral devices. This allows application processes to be connected to various displays without having to re-develop the entire system.

Toshiba offers a range of these bridge ICs. They are suitable for consumer, industrial and automotive applications such as smartwatches, tablet PCs, ultrabooks, 4K UHD displays, smart TVs, wearables, cameras, gaming accessories, head-mounted displays (HDMs), LCDs, IO port expansions or POS applications.

The DSI-LVDS bridge enables ICs to control an LVDS-compatible display via a DSI link. These support a pixel resolution of 24 bits. The TC358771XBG and TC358774XBG models enable classic 4:3 (UXGA, Ultra Extended Graphics Array) with a resolution of 1600 × 1200 pixels over DSI Single Link. The TC358772XBG and TC358775XBG models support WUXGA (Wide Ultra eXtended Graphics Array), which enables displays with 16:10 format and a resolution of 1920 × 1200 pixels over DSI Dual Link. The bridge ICs also support an I2C master controlled by the DSI link that can be used as an interface with other control functions via I2C.

The bridge ICs operate using the LVDS standard at 135MHz, while in the DSI standard they transmit at up to 1Gbit/s per lane. They support the video input formats RGB565/666/888. By optimizing the backlighting of LCD displays based on ambient light, they help to reduce the power usage of mobile devices.


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Figure 1: An Embedded Clock Serializer with a Single LVDS Channel
Figure 1: An Embedded Clock Serializer with a Single LVDS Channel